The subject matter of the present invention relates to an electrodeposited photoresist and a dry film photoresist hybrid photolithography process for printed circuit board patterning.
The manufacture of Printed Circuit Boards (PCB) includes a subtractive etching process. The subtractive etching process further includes a photolithography process. As a result of the photolithography process, the PCB has been fully copper plated which means that the entire external surface of the PCB has been plated with copper; as a result, the drilled ‘through holes’ in the PCB have been plated with copper. Normally, a layer of dry film resist is applied to the copper layer which covers the external surface of the PCB. At this point, the next step is to: expose an image that will be etched into the panel of the PCB, develop the photoresist, and etch the copper that is not wanted. This is the ‘subtractive’ portion of the process wherein the process includes subtracting any unwanted copper from the final product. Then, in connection with the remaining copper that is wanted on the panel of the PCB, the photoresist is stripped from the remaining copper that is wanted on the panel. In order for the PCB to be reliable in terms of its functionality, the ‘plated through holes’ in the PCB need to be robust; that is, in each of the ‘plated through holes’, there needs to be an electrical connection between a circuitized image on one surface of the panel and any other interplaying connections on the PCB. In order for the ‘plated through holes’ to be reliable in terms of their functionality, after the circuitization process, all of the copper in each of the ‘plated through holes’ should remain in place. That is, if any etchant (which was used to etch the copper on the external surface of the PCB) should get into the ‘plated through hole’, that etchant would remove the copper from the ‘plated through hole’ (as it would in connection with the copper on the external surface of the PCB). If the etchant did, in fact, remove some copper from the ‘plated through hole’, a defect could be seen on the external surface of the PCB panel. One such defect is known as a “rim void”. An annular ring, known as a ‘land’, is disposed around each of the ‘plated through holes’ on the external surface of the PCB. If any damage is done to the photoresist that is covering the aforementioned ‘land’, or if there is no photoresist on the aforementioned ‘land’ for some reason, damage would exist on the copper associated with that ‘land/annular ring’. That is, since at least some of the photoresist was not present on the aforementioned land/annular ring, it is assumed that the etchant was able to enter the ‘plated through hole’ and, to some degree, etch-out the barrel of the ‘plated through hole’. The aforementioned damage to the ‘land/annular ring’, where the outerlayer annular copper ring (or land) surrounding the ‘plated through hole’ has been compromised by etchant solution, is known as a ‘rim void’. More than likely, that ‘rim void’ damage to the ‘plated through hole’ is a scrappable defect. If the ‘rim void’ progresses into the ‘plated through hole’, copper etchant solution has definitely infiltrated the ‘plated through hole’ and may have etched a significant portion of the hole plating away causing an instantaneous or latent electrical open-circuit. Therefore, in the prior art, the higher the number of ‘plated through holes’ on a PCB, the higher the number of ‘rim voids’ which may exist (where the photoresist covering the ‘lands’ around the ‘plated through holes’ is damaged) on the ‘lands/annular rings’ around the ‘plated through holes’ of the PCB.
The following patent application set forth below in item number (1) and the following eight (8) patents set forth below in items (2) through (8) are all incorporated herein by reference into the specification of this application:
(1) U.S. Patent Application Publication No. US 2002/0100608, published Aug. 1, 2002, to Fushie et al, entitled “Multilayer Printed Wiring Board and a Process of Producing Same”;
(2) U.S. Pat. No. 6,339,197 B1, issued Jan. 15, 2002, to Fushie et al, and entitled “Multilayer Printed Circuit Board and the Manufacturing Method”;
(3) U.S. Pat. No. 5,780,143, issued Jul. 14, 1998, to Shimamoto et al, and entitled “Circuit Board”;
(4) U.S. Pat. No. 5,758,413, issued Jun. 2, 1998, to Chong et al, entitled “Method of Manufacturing a Multiple Layer Circuit Board Die Carrier with Fine Dimension Stacked Vias”;
(5) U.S. Pat. No. 5,699,613, issued Dec. 23, 1997, to Chong et al, entitled “Fine Dimension Stacked Vias for a Multiple Layer Circuit Board Structure”;
(6) U.S. Pat. No. 5,542,175, issued Aug. 6, 1996, to Bhatt et al, entitled Method of Laminating and Circuiting Substrates Having Openings Therein;
(7) U.S. Pat. No. 5,443,672, issued Aug. 22, 1995, to Stoll et al, entitled “Process for Coating Circuit Boards”; and
(8) U.S. Pat. No. 4,783,247, issued Nov. 8, 1988, to Seibel, entitled “Method and Manufacture for Electrically Insulating Base Material Used in Plated-through Printed Circuit Panels”.